Advanced computer architecture 

UNIT I

11.  Explain the hybrid approach for encoding an instruction set?

The hybrid approach reduces the variability in size and work of the variable architecture but provide multiple instruction lengths to reduce code size. 

12.  What are the registers used for MIPS processors.

MIPS has 34, 64-bit general purpose registers (GPRs), named R0, R1…R31. GPRs are sometimes called as integer registers. There are also a set of 32 floating point registers (FPRs), named F0,F1….F31, which can hold 32 single precision values and 32 double precision values. 

13.  Explain the concept behind pipelining.

Pipelining is an implementation technique whereby multiple instructions are overlapped in execution. It takes advantage of parallelism that exists among actions needed to execute an instruction. 

14.  Write about pipe stages and processor cycle.

Different steps in an instruction are completed in different parts of different instruction is parallel. Each of these steps is called a pipe stage or pipe segment.  The time required between moving an instruction one step down the pipeline is called processor cycle. 

15.  Explain pipeline hazard and mention the different hazards in pipeline.

Hazards are situations that prevent the next instruction in the instruction stream from executing during its designated clock cycle. Hazards reduce the overall performance from the ideal speedup gained by pipelining. The three classes of hazards are,

• Structural hazards.

• Data hazards.

• Control hazards. 

16. Explain the concept of forwarding.

Forwarding can be generalized to include passing a result directly to the functional unit that fetches it. The result is forwarded from the pipeline register corresponding to the output of one unit to the input of the same unit.  

17. Mention the different schemes to reduce pipeline branch penalties.

a. Freeze or flush the pipeline

b. Treat every branch as not taken

c. Treat every branch as taken 

d. Delayed branch

18. Consider an unpipelined processor.

Assume that it has a 1ns clock cycle and that it uses 4 cycles for ALU operations and branches and 5 cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively.

Suppose that due to clock skew and setup, pipelining the processor adds 0.2 ns of overhead to the clock.

Ignoring any latency impact, how much speedup in the instruction execution rate will we gain from a pipeline? 

The average instruction execution time on an unpipelined processor is  = clock cycle x Average CPI = 1 ns x ((40% x 4)+(20 x 4)+(40 x 5)) = 4.4 ns.

The average instruction execution time on an pipelined processor is  = 1+0.2ns = 1.2ns  Speedup = Avg. instruction time unpipelined/ Avg. instruction time pipelined = 4.4/1.2 = 3.7 times. 

19. Briefly explain the different conventions for ordering the bytes within a larger object?

Little endian byte order puts the byte whose address is “x….x000” at the least significant position in the double word. Big endian byte order puts the byte whose address is “x….x000” at the most significant position in the double word. 

20. When do data hazards arise? 

Data hazards arise when an instruction depends on the results of a previous instruction in a way that is expressed by the overlapping of instructions in the pipeline.