Instruction-level parallelism in EPIC
Static Multiple Issue : The VLIW Approach
Very long instruction word (VLIW) refers to processor architectures
designed to take advantage of instruction
level parallelism (ILP). Whereas conventional processors
mostly allow programs only to specify instructions that will be executed in
sequence, a VLIW processor allows programs to explicitly specify instructions
that will be executed at the same time (that is, in parallel).
Modern superscalar processors are
complex, power-hungry devices that present an antiquated view of processor
architecture to the programmer in the interests of backwards compatibility —
and do a lot of work to achieve high performance while maintaining this
illusion.
The alternative to superscalar is
aVLIW architecture, but these have traditionally been actively
backwards-incompatible, with performancehighly dependent on the (frequently
mediocre) abilities ofthe compiler. Neither VLIW nor superscalar are perfect
architectures:
each has its own set of
trade-offs. This report discusses the relative strengths and weaknesses of the
two, focusing on the benefits of VLIW andthe closely-related EPIC architecture
as used in Intel’s Itanium processor family.An introduction to the motivation
behind VLIW is given, VLIWand EPIC are discussed in detail,and then two case
studies are presented: the Analog Devices SHARC family of DSPs, demonstrating
the VLIW influences present in a modern DSP; and Intel’s Itanium processor
family, which is to date the only implementation of EPIC
VLIWs use multiple,
independent functional units. Rather than attempting to issue multiple,
independent instructions to the units, a
VLIW packages the multiple operations into one very
long instruction, or requires that the
instructions in the issue packet satisfy the same constraints.
