IA-64 Architecture

IA-64 is a load/store architecture, with 64-bit memory addresses and registers. There are 128 64-bit general-purpose registers, 128 82-bit floating point registers, 64 1-bit predicate registers  and 8 64-bit branch registers (used to hold branch destination addresses). There are also assorted control registers that we will not concern outselves with. Intel have chosen to use a RISC 2-style register stack with some modifications. The first 32 registers are global, and the remainder are allocated to procedures/functions. The size of the block of registers allocated to a procedure/function is variable. Also, instead of overlapping blocks of registers, the calling procedure's first local register is used as a pointer to a block of the called procedure's local registers for passing parameters.

-64 divides instructions up into groups and bundles. A group is a sequence of instructions that could in principle be executed in parallel provided:

• Sufficient Hardware is Available — Clearly, it is expected that later processors will have more hardware and will be able to execute a larger number of instructions simultaneously.
• No Memory Dependencies — The compiler will guarantee that there are no data dependencies between registers that prevent execution, but the hardware must check dependencies in memory. This comes back to the problem of aliasing of memory addresses.

• I — ALU and non-ALU Integer — These include the usual integer arithmetic/logical operations, together with various moves, tests and shifts.
• M — ALU and Memory — These also include interger arithmetic/logical operations, together with memory access.
• F — Floating point — Obviously, floating point operations.
• B — Branches — Branches and procedure calls. The branches contain static prediction information which is used until the branch prediction algorithm builds up enough history information.
• L+X — Extended — Various other things.

 Predication

Another aspect of IA-64 that is interesting — though not really new, as a simpler version appeared in the ARM² architectures — is a way of dealing with (some) conditional branches forming without needing to flush the pipeline or predict their outcome.
The way it works is that each instruction is conditional. That is, it is only executed if a specific condition, or predicate is true. The IA-64 architecture includes a set of 64 1-bit predicate registers. Comparison instructions can be used to set and clear these predicate registers, and subsequent instructions are conditionally executed, depending on their values