Dynamic
Scheduling Using Tomasulo’s Approach :
Tomasulo's
algorithm implements register renaming through the use of what are called reservation
stations. Reservation stations are buffers which fetch and store
instruction operands as soon as they are available
In
addition, pending instructions designate the reservation station that will
provide their input. Finally, when successive writes to a register overlap in
execution, only the last one is actually used to update the register. As
instructions are issued, the register specifies for pending operands are
renamed to the names of the reservation station, which provides register
renaming.
the
basic structure of a Tomasulo-based MIPS processor, including both the
floating-point unit and the load/store unit.
Instructions
are sent from the instruction unit into the instruction queue from which they
are issued in FIFO order.
The
reservation stations include the operation and the actual operands, as well as
information used for detecting and resolving hazards. Load buffers have three
functions: hold the components of the effective address until it is computed,
track outstanding loads that are waiting on the memory, and hold the results of
completed loads that are waiting for the CDB.
Similarly,
store buffers have three functions: hold the components of the effective addr
ess until it is computed, hold the destination memory addresses of outstanding
stores that are waiting for the data value to store, and hold the address and
value to store until the memory unit is available.
All
results from either the FP units or the load unit are put on the CDB, which
goes to the FP register file as well as to the reservation stations and store
buffers. The FP adders implement addition and subtraction, and the FP
multipliers do multiplication and division.
